Buried contact regions within semiconductor integrated circuits have been extensively used for connecting polysilicon elements to silicon substrate elements where needed. The following U.S. Patents discuss buried contact regions.
1. U.S. Pat. No. 5,064,776, by Roberts, "Method of Forming Buried Contact Between Polysilicon Gate and Diffusion Area". PA1 2. U.S. Pat. No. 5,126,285, by Kosa et al., "Method for Forming a Buried Contact". PA1 3. U.S. Pat. No. 5,348,896, by Lee, "Buried Contact Process". PA1 4. U.S. Pat. No. 5,162,259, by Kolar et al., "Method for Forming a Buried Contact in a Semiconductor Device ,". PA1 1. Forming an active area by forming a SiO.sub.2 layer and Si.sub.3 N.sub.4 layer thereafter on the substrate. PA1 2. P-well and N-well are formed on surface of the substrate. PA1 3. Field Oxide (FOX) is formed for isolation purpose by a conventional LOCOS process. PA1 4. The threshold voltage (Vt) adjustment process is performed by implanting ions on the active area. PA1 5. Gate oxide is grown on the active area. PA1 6. Substantially 500 A thickness of thin polysilicon deposition is performed. PA1 7. The buried contact region is patterned by photolithography. PA1 8. The thin polysilicon layer and gate oxide unprotected by the photoresist are dry and wet etched away to form a buried contact. PA1 9. The photoresist is removed. PA1 10. A thick polysilicon layer is then deposited. PA1 11. Using a diffusion process, the polysilicon layer is doped with phosphorous oxychloride (POCl.sub.3) to reduce its resistance. Meanwhile, phosphorous doping penetrates the interface between polysilicon and silicon to form a junction at the buried contact. PA1 12. Polysilicon or polycide (Tungsten silicide) gate is patterned and the unprotected area is removed by anisotropically dry etch to form the gate. PA1 13. The photoresist is removed.
With reference to FIG. 1 through FIG. 4, a conventional process forming a buried contact of a CMOS SRAM cell is depicted as follows.
The resulting structure of the above processes is shown in FIG. 1 and further undergone the following processes.
The resulting structure of the above three processes is shown in FIG. 2 and further undergone the following processes.
The resulting structure of the above four processes is shown in FIG. 3 and undergoes further conventional processes. The formation of the trench shown in FIG. 3 is caused by misalignment between the buried contact and the polysilicon gate, and similarly in etching selectivity of the polysilicon and silicon substrate. The further conventional processes include forming a Source/Drain region, a TEOS (Tetra-Ethyl-Ortho-Silicate) SiO2 layer, poly2, a Borophosphosilicate Glass (BPSG) dielectric layer, contact (Tungsten plug), a metal layer and passivation layer. The final resulting structure is shown in FIG. 4. In FIG. 4, an undesired trench is formed around the buried contact.
It is found that cell the shown in FIG. 4, which is the result of the conventional approach, fails sometimes due to open and junction leakage caused by the trench between the N+ junction and junction of buried contact.
As the technology goes to the deep sub-micron era, the thermal budget is reduced and the POCL.sub.3 concentration is decreased because of a thinner gate oxide. The opening (trench) between the N+ junction and buried contact junction and leakage of the buried contact become worse.
Therefore, it is a main object of the invention to provide a method of forming a self-aligned buried contact without trench, which overcome the drawbacks of the conventional approaches.